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FASTPULSE HIGH SPEED LAN TRANSCEIVERS
High performance transceivers for ATM 155 Mbps, 100Base-TX, and TP-FDDI Integrated drop-in frontend solution Footprint compatible with popular LCF 9-pin Fiber Optic Transceivers
Part Number Chart
Part Number PE-68531G PE-68532G, PE-68538G PE-68537G
Note: Also available without metallic case: use suffix "C", eg. PE-68532C.
Application TP-FDDI ATM 155 Mbps 100Base-TX
Standard ANSI X3T12, TP-PMD ATM-UNI-PMD STS-3c IEEE 802.3u PMD
General Description
The FASTPULSE high speed LAN transceivers provide high performance, cost-effective solutions for ATM 155 Mbps, TPFDDI and Fast Ethernet 100Base-TX frontends. The transceivers interface the standard "fiber" PECL interface to UTP-5 cable, integrating the transceiver IC, magnetics and connector in the process. The highly compact design implements the entire Physical Media Dependent (PMD) circuit in the standard 9-pin form factor, which reduces component count and board space. This modular transceiver approach, minimizes the design effort and risk of implementing 100 Mbps + frontends. Employing FASTPULSE technology, these transceivers integrate the full transmit/receive interface functions of signal encoding/ decoding, adaptive equalization, DC restoration, signal filtering, and isolation. This integrated approach, coupled to the novel circuit design, results in a high performance frontend which eliminates many of the conventional design compromises and parasitic elements which plague high speed designs. The long design cycle of selecting and optimizing the sensitive analog IC/magnetic frontend is essentially replaced with a single-shot, single-device approach. The compact 9-pin footprint matches the industry standard 9-pin LCF fiber optic transceivers (AMP, HP, etc.), allowing a common board design to accommodate both fiber and copper options. The transceiver also allows existing fiber designs to be upgraded for UTP support with minimal design effort. The PE68531G is a TP-FDDI transceiver which adheres to the ANSI TP-PMD standard and employs MLT3 signaling to support 100 Mbps (125 Mbaud) over 100 m UTP-5 cable. The PE68532/38G are ATM transceivers which adhere to ATM-UNIPMD standard and employ NRZ signaling to support 155 Mbps over 100 m UTP-5 cable. The PE-68532G is configured for the adapter node of a network and the PE-68538G for the switch or hub node. The PE-68537G is a 100Base-TX transceiver which adheres to IEEE802.3u standard and employs MLT3 signaling to support 100 Mbps (125 Mbaud) over 100 m of UTP-5 (2-pair) cable.
Features
s UTP Transceivers for ATM 155 Mbps, TP-FDDI and 100Base-TX s Drop in replacement for standard 9-pin fiber optic transceivers s Full compliance with PMD standards: ATM, ANSI and IEEE s Supports 100 m of Unshielded Twisted Pair, Category 5 cable s Implements full adaptive equalization and baseline wander correction s Excellent transmit and receive jitter performance s EMC optimized design provides for low emissions and high immunity (ESD protection per IEC 801) s Direct PECL logic interface to PHY layer chip sets s Offers simple, low-cost upgrade from existing fiber designs s Offers flexibility of single UTP/fiber board s Compact footprint enables efficient single/multiport designs s 1500 Vrms voltage isolation s Wavesolder and aqueous wash compatible s ISO 9001 quality s Two package options: with metallic case "G" and without case "C"
Applications
The following products for ATM 155, TP-FDDI or 100Base-TX:
s s s s s s s s Network adapter cards (ISA, PCI, VME etc.) Hubs or concentrators Motherboards (PC, workstation, industrial) Bridges, routers, switches Switch uplink modules LAN analyzers/test equipment Point to point links (Telecom) www..com Peripherals: storage, print servers, etc.
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Block Diagram
STAKE POST
GND 1 RD+ 2 RD- 3 SD+ 4 VCC 5 VCC 6 TD- 7 TD+ 8 GND 9 ENCODER (MLT3/NRZ) 1
TRANSMIT AMPLIFIER
AGC AMPLIFIER
SHIELD
7
T E R M I N A T I O N
SIGNAL DETECT
6 5 4 3 2 1
FILTER & TERMINATION
STAKE POST
SHIELD
Notes: 1. PE-68531/37G implement MLT3. PE-68532/38G implement NRZ 2. Dotted line indicates the transceiver IC function. 3. RJ-45 pinout shown is for PE-68531/32G. See pinout specifications for PE-68537/36G.
Functional Description
The key functions of the transceivers are outlined in the block diagram above. In the transmit channel, the PECL (100 K) signals from the PHY chip set (TD) are encoded to appropriate line coding and driven out differentially by the edge-controlled transmit amplifier in the transceiver IC. The wideband transformer provides the required 1500 V isolation and the common mode choke eliminates high frequency common mode noise. The magnetics are tuned specifically to the characteristics of the transceiver IC to give a highly balanced system with optimum signal rise-time, minimum jitter and low emissions. The transformers exhibit a high minimum inductance in order to counter signal droop in the presence of DC bias. The outputs are fully terminated with cable impedance (100 ) to meet return loss specification. See electrical characteristics section for full transmitter specifications. In the receive channel, the incoming differential signal from the cable passes through a wideband isolation transformer and the choke, before being filtered and terminated for high frequency noise rejection. The resulting differential signal is fed to transceiver IC for adaptive equalization, baseline restoration and line decoding. Adaptive equalization is necessary to compensate for the frequency dependent attenuation and phase distortion which the signal suffers in the cable. The optimum compensation required will vary with cable length and so a high performance adaptive equalizer is employed which constantly adjusts itself by means of a data quantized feedback loop. The equalizer characteristics reflect the EIA/TIA 568 cable standard and extensive modeling of UTP-5 cable characteristics under real life conditions. The operation of the equalizer can be seen in the performance section. The baseline restoration loop performs a DC restoration on the incoming signal (as defined in ANSI TPPMD recommendation) which may occur due to data pattern dependent DC shifts and the inherent low frequency bandwidth limitations of the channel and AC coupling transformers. If not corrected, this DC drift (or baseline wander) can cause degradation in signal/noise ratio and can result in data errors. The baseline restoration loop in the transceiver constantly monitors the incoming signal and restores the DC level to a nominal level. The resulting amplified, equalized and DC restored signal is decoded in the line decoder as per appropriate scheme and driven out as differential 100 K PECL signals RD. See electrical characteristics section for full receiver specifications. The signal detect function monitors the equalized incoming signal to notify PHY controller that a valid signal is received. This is explicitly required by the TP-FDDI specification and is optional for ATM system designers. The SD signal is driven out as singleended PECL signal. The unused signal pairs in the RJ-45 are terminated at their common mode impedance to minimize EMI emissions.
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SHIELDED RJ-45 CONNECTOR
BASELINE RESTORATION
DECODER (MLT3/NRZ) 1
ADAPTIVE EQUALIZER
FILTER & TERMINATION
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FASTPULSE HIGH SPEED LAN TRANSCEIVERS
System Application
ATM155/100Base-TX
PHYSICAL CONTROLLER
DECODER
FRAMING
SERIAL TO PARALLEL
PMD TRANSCEIVER
MEDIA
TWISTED PAIR
CLOCK RECOVERY CLOCK GENERATION
RD
FASTPULSE
TD
ENCODER
FRAMING SYNC.
PARALLEL TO SERIAL
NRZ DATA (PECL)
Notes: ATM Controllers: Texas Instruments, PMC, Fujitsu, AMCC . . . 100BTX/FDDI Controllers: National Semiconductor, AMD, Motorola . . .
The transceiver provides all Physical Media Dependent (PMD) functions required to allow digital Physical layer controller to send/receive data integrally over the twisted pair media. The TP-FDDI/100Base-TX PHY chip set will perform clock recovery/generation, scrambling, 4B/5B codec, serial-parallel conversion, etc. These functions are available from several vendors in different chip set partitioning. Please refer to vendor list in appendix for more information. The PECL interface is a standard interface used by fiber optic transceivers in FDDI and 100Base-FX applications. Since 100Base-TX employs the basic TP-FDDI PMD scheme, the PE-68531G and PE-68537G are electrically identical with different RJ-45 pinouts as per the standards (refer to pinout specification). The PE-68537G fits the
following Fast Ethernet product architectures: 100Base-TX only with adapter and repeater, 10/100 adapter with separate 10/100 RJ-45 connectors. The ATM PHY chip set will perform clock recovery/generation, serial-parallel conversion, framing, scrambling, cell extraction/ insertion, etc. These functions are available from several vendors in different chip set partitioning. The PECL interface is a standard interface used by fiber optic transceivers in ATM applications. The PE-68532G and the PE-68538G are electronically identical but have "mirror" RJ-45 pinouts as required by standard for adapter (user) node and switch (hub) node of network respectively (refer to pinout specification).
Pin Descriptions Signal Pin #
GND RD+ RDSD+ Vcc Vcc TDTD+ GND 1 2 3 4 5 6 7 8 9
RJ-45 Connector Pinout I/O
-- O O O -- -- I I --
Description
Analog Ground Differential Receive Data + Differential Receive Data Signal Detect Output Power Supply Voltage Power Supply Voltage Differential Transmit Data Differential Transmit Data + Analog Ground
Type
Supply PECL PECL PECL Supply Supply PECL PECL Supply
Pin # PE-68531/32G
1 2 3 4 5 6 7 8 Transmit (TX+) Transmit (TX-) Unused P1 Unused P2 Unused P2 Unused P1 Receive (RX+) Receive (RX-)
PE-68537G
Transmit (TX+) Transmit (TX-) Receive (RX+) Unused P1 Unused P1 Receive (RX-) Unused P2 Unused P2
PE-68538G
Receive (RX+) Receive (RX-) Unused P1 Unused P2 Unused P2 Unused P1 Transmit (TX+) Transmit (TX-)
Note: Unused pairs (P1, P2) are terminated onboard
Note: Two Mechanical Stake Posts are connected to RJ-45 Shield and Body Shield.
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Application Circuit
+5 V
PHY CHIPSET
82
RECEIVE DATA
82
130 +5 V 82
SIGNAL DETECT
130
1 2 3
GND RD+
68 +5 V
4 5 100 nF 82 82 6 7 8 9
SD+ VCC VCC TDTD+ GND
FASTPULSE
130
180
TRANSMIT DATA
130
130
SIGNAL GROUND PLANE
CHASSIS GROUND PLANE
BACKPLATE
Application Notes
1. The PECL termination networks shown (Thevenin 50 ) are typical. Signal traces should be effective for 50 transmission lines. Other suitable termination schemes may be used. 2. Place ter mination networks near input data pins of Transceiver (TD) and PHY device (SD, RD) for optimum termination. 3. Make all differential signal paths short and the same length to avoid unbalancing effects and unwanted loops. 4. For chip sets with differential SD inputs, the unused SD signal can be terminated as shown. 5. VCC signals may be connected together at transceiver as shown. Decouple very close to transceiver. 6. Use low inductance, ceramic SMD bypass capacitors and optional ferrite inductors for optimum high frequency decoupling. 7. Device ground pins should be directly connected to low impedance ground plane for signal return current. 8. Use multi-layer PCB type with dedicated GND and VCC layers for best high frequency and EMC performance. At least four layers are recommended with outside layers for signal routing and inner layers for supply planes. 9. Use of ground plane partitions, as indicated, is recommended for best EMC performance. The signal ground plane extends back to controller from edge of transceiver. The chassis ground plane extends to media side of board and is generally connected directly to the backplate. 10. RJ-45 flanges should make galvanic contact to backplate cutout. Stake posts should be soldered to chassis plane for best EMC performance. Refer to EMC section for further EMC considerations.
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RJ-45 CONNECTOR
RD-
FASTPULSE HIGH SPEED LAN TRANSCEIVERS
Performance
The following eye pattern measurements show the operation of the adaptive equalizer and indicate the jitter performance of the transceivers. All jitter measurements shown are peak values resulting from combination of Transmit, Receive and cable contributions. Figure A shows the MLT3 transmit output waveform for 0 m cable. Figure B shows the waveform at receiver input after massive attenuation and phase distortion effects of 100m UTP-5. Figure C shows the recovered NRZI data for the same signal. The same measurements are repeated in Figures D, E, and F for ATM 155 Mbps NRZ signal.
TP-FDDI/100Base-TX (PE-68531G/37G)
MLT3 Transmit Output (TX) Receiver Input (RX) NRZI Receiver Output (RD)
A
0 Meter UTP-5 Cable 500mV/DIV, 2ns/DIV
B
100 Meter UTP-5 Cable 200mV/DIV, 2ns/DIV
C
100 Meter UTP-5 Cable 200mV/DIV, 2ns/DIV
ATM-155 (PE-68532G/38G)
NRZ Transmit Output (TX) Receiver Input (RX) NRZI Receiver Output (RD)
D
0 Meter UTP-5 Cable 200mV/DIV, 2ns/DIV
E
100 Meter UTP-5 Cable 100mV/DIV, 2ns/DIV
F
100 Meter UTP-5 Cable 200mV/DIV, 2ns/DIV
Notes: The PE-68531G/68537G MLT-3 transmit eye pattern is optimized for minimum overshoot (< 3%) and a 3.5 ns rise time. It has < 1 ns transmit jitter and as a result of its fast rise time, the receive eye pattern has < 2 ns of jitter at 100 meters. Similarly, the PE-68532G/38G NRZ transmit eye pattern has a 3 ns rise time, < 5% overshoot and less than 1 ns of transmit jitter. Due to its relatively fast rise time and low transmit jitter, the data dependent jitter from the channel is < 1.6 ns at the receiver output as
shown. There is a trade-off design choice: A faster rise time will minimize jitter and produce a low bit error rate (BER). In contrast, a fast rise time, while reducing jitter, can produce excessive overshoot and EMI emissions when the signal encounters impedance mismatches in the cable or punch down blocks. The transceivers have been optimized and tested to provide optimum balance between low BER and minimum emissions.
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Electrical Characteristics
Absolute Maximum Ratings Parameter
Supply Voltage Input Voltage Lead Solder Temp/Time
Symbol
Vcc VI --
MIN
0 GND - 0.3V --
Typical
-- -- --
MAX
6.0 Vcc + 0.3 240/10
Units
V V C/S
Recommended Operating Conditions
Supply Voltage Supply Current Operating Temperature Storage Temperature Vcc Is TA Ts 4.75 -- 0 - 40 5.0 170 25 -- 5.25 200 70 +125 V mA C C
Transmitter Input Characteristics
PECL High Level Input PECL Low Level Input TD+/-VIH TD+/-VIL Vcc--1170 Vcc--1950 -- -- Vcc--720 Vcc--1440 mV mV
Transmitter Output Interface -- PE-68531G/37G
Transmit Signal Level 1 Rise Time (10%-90%) Fall Time (10%-90%) Total Peak-Peak Jitter 2 Vo TR TF -- 1.90 3.0 3.0 -- 2.00 3.4 3.4 0.5 2.1 5.0 5.0 1.0 Vpp ns ns ns
Transmitter Output Interface -- PE-68532G/38G
Transmit Signal Level 1 Rise Time (10%-90%) Fall Time (10%-90%) Total Peak-Peak Jitter Vo TR TF -- 0.94 1.5 1.5 -- 1.00 2.8 2.8 0.5 1.06 3.5 3.5 1.0 Vpp ns ns ns
Receiver Output Interface -- PE-68531G/37G & PE-68532G/38G
PECL High Level Output 3 PECL Low Level Output 3 PECL Output Voltage Swing Rise Time (10%-90%) Fall Time (10%-90%) Total of Peak-Peak Duty Cycle Distortion and Data Dependent Jitter 2 RD VOH RD VOL VOH -VOL TR TF PE-68531G/37G PE-68532G/38G Vcc--1220 Vcc--1950 600 0.3 0.3 -- -- -- -- -- 0.7 0.7 1.5 1.0 Vcc--720 Vcc--1600 -- 1.2 1.2 2.5 2.0 mV mV mV ns ns ns ns
Signal Detect Output -- PE-68531G/37G & PE-68532G/38G
PECL High Level Output 3 PECL Low Level Output 3 SD+/VOH SD+/VOL Vcc--1220 Vcc--1950 -- -- Vcc--720 Vcc--1600 mV mV
Part Number
PE-68531G/7G PE-68532G/38G
Overshoot (MAX)
50mV 50mV
Return Loss (TX, RX) 1-60 MHz
-16 dB -16 dB
Voltage Isolation
1500 VRMS 1500 VRMS
Bit Error (MAX)
10 -12 10 -10
Power Dissipation (mW MAX)
1000 1000
Transformer Inductance (0-8mADC Bias)
350 H 350 H
Signal Detect (S MAX) Assert De-assert
1000 1000 350 350
60-100 MHz
-12 dB -12 dB
Notes: 1. Transmit signal level is differential and measured with a 100 differential load between pins 1 and 2 of the RJ-45.
2. Including jitter from the transmitter cable and receiver. 3. Measured with standard PECL load, 50 to VCC-2 V.
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FASTPULSE HIGH SPEED LAN TRANSCEIVERS
Mechanicals
FASTPULSE-G
FRONT OF PANEL
1.550 .030 39,37 0,76 .575 .005 14,61 0,13 .656 .005 16,66 0,13 .150 3,81
Weight . . . . . . . . . . .15 grams Tray . . . . . . . . . . . . . . .36/tray
FASTPULSE
.484 .005 12,29 0,13 .630 16,00
PE-6853XG
IRELAND
.995 .020 25,27 0,51
TOP OF MOTHER BOARD TO BOTTOM OF OPENING
.078 .005 1,98 0,13
PANEL CUTOUT
Inches mm Unless otherwise specified all tolerances are .010 0,25 Dimensions:
DATE CODE
.500 12,70
.550 13,97
.600 15,24
.100 .005 2,54 0,13 .020 .010 X 0,51 .0,25 .800 .005 20,32 0,13 .150 .010 3,81 0,25 .800 20,32 .510 12,95
.160 4,06 .062 .005 DIA 1,57 0,13 2 SOLDER POSTS
.800 .010 20,32 0,25
FASTPULSE-C
FRONT OF PANEL
1.520 .020 38,61 0,51 .150 3,81 .656 .005 16,66 0,13
.575 .005 14,61 0,13
IRELAND
FASTPULSE PE-6853XC
.970 .020 24,64 0,51
.450 11,43
.630 16,00
.484 .005 12,29 0,13
.080 2,03
DATE CODE
1.335 .020 33,91 0,51 1.075 .020 27,31 0,51 .740 18,80
TOP OF MOTHER BOARD TO BOTTOM OF OPENING
.078 .005 1,98 0,13
PANEL CUTOUT
.280 .020 7,11 0,51
.150 .010 3,81 0,25
.550 .600 13,97 15,24
.100 .005 2,54 0,13 .800 .005 20,32 0,13 .020 .010 0,51 X 0,25 9 PINS
.800 20,32
.510 12,95
.160 4,06
Dimensions:
Inches mm
.800 .010 20,32 0,25 .062 .005 DIA 1,57 0,13 .094 .005 2 SOLDER POSTS 2,39 0,13 DIA 2 SOLDER POSTS
.050 1,27
Unless otherwise specified,all tolerances are
.010 0,25
Weight . . . . . . . . . . .15 grams Tray . . . . . . . . . . . . . . .36/tray
Notes: 1. Pin composition is 60/40 tin/lead phosphor bronze. 2. This device contains active components and standard ESD precautions should be employed in handling the device. 3. Components on underside have maximum height of .030" (0,76 mm), less than standoff height of .050" (1,27 mm) as determined by pins/supports. This ensures the recommended .020" (0,51 mm) wash clearance height. For safety, there should be no exposed signal routing used under the device.
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EMC Considerations
The FASTPULSE high speed LAN transceiver has been designed and tested to minimize EMI emissions and maximize its immunity. Some of the key measures employed on the transceivers are as follows: s Multi-Layer board design, with optimized ground plane partitioning s Edge-Rate control on transceiver IC outputs and signal filtering s High-Performance magnetics tuned to transceiver silicon s Galvanic shield formed from RJ-45 shield, body shield and connected to stake posts for direct chassis ground connection s Onboard termination of unused cable pairs to chassis ground s Extensive on-board decoupling of power signals s Integrated design eliminates board parasitic effects These built-in measures ease the difficult task normally facing the designer. Nevertheless, it is still crucial to employ good high speed PCB design rules in laying out the board, as outlined in the application section. Physical shielding is an important factor in further minimizing emissions. The shielded RJ-45 connector has flared extensions which are intended to form a galvanic connection to cutout in the backplate. The backplate is typically connected to chassis ground. The body shield (G version) is further connected to the RJ-45 shield and the two mechanical stake posts. These should be soldered directly to the chassis ground. This chassis grounding scheme will minimize EMI emissions and also provide a direct discharge path to ground for ESD discharges to the exterior of the device, in line with IEC801 requirements. As an indication, the graph below shows typical EMI measurements obtained on a standard setup. It should be noted that EMC performance is a system measurement and very implementation specific.
Typical EMI Field Strength (ATM-155)
70
Typical EMI Field Strength (100Base-TX)
70
FIELD STRENGTH (dBV/m)
FCC A 50 FCC B 40 30 20 10 30 200 CISPR B CISPR A
FIELD STRENGTH (dBV/m)
60
60 FCC A 50 FCC B 40 30 20 10 30 200 CISPR B CISPR A
FREQUENCY (MHz)
FREQUENCY (MHz)
Note: PE-68532G in standard ATM 155 system @ 3 m, anechoic chamber. Contact Pulse for further setup details if required.
Note: PE-68537G in standard 100-TX system @ 3 m, anechoic chamber. Contact Pulse for further setup details if required.
For More Information :
Corporate
12220 World Trade Drive San Diego, CA 92128 Tel: 619 674 8100 FAX: 619 674 8262 http://www.pulseeng.com Quick-Facts: 619 674 9672
Europe
1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44 1483 401700 FAX: 44 1483 401701
Asia
150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65 287 8998 FAX: 65 280 0080
Distributor
Information furnished in this data sheet is believed to be accurate. However, no responsibility is assumed by Pulse for its use or for any infringements of patents or other rights of third parties which may result from its use. Data is subject to change without notice. Companies or products mentioned in this document, other than Pulse, are trademarks of the respective companies or their products. Printed on recycled paper. (c)1999, Pulse Engineering, Inc.
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H309.A (7/96)

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